1. Field
Exemplary implementations of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor chip, a semiconductor integrated circuit including the semiconductor chip, a semiconductor system including the semiconductor integrated circuit, and a method of driving the semiconductor system.
2. Description of the Related Art
Generally, a packaging technology of a semiconductor integrated circuit has been continuously developed to satisfy a demand for miniaturization of the semiconductor integrated circuit and mounting reliability thereof. Recently, various technologies of a stack package have been developed to satisfy a demand for small-sized and multi-functional electric/electronic products.
The “stack” used in a semiconductor industry refers to vertically stacking at least two semiconductor chips or packages. For example, in the case of a semiconductor memory device, a product having a memory capacity twice or more than a memory capacity which may be implemented during a semiconductor integrated process may be implemented by a stack package. Further, since the stack package may have advantages, such as the increase in memory capacity, the use efficiency of mounting density and mounting area, and the like, a research and development for the stack package has been accelerated.
The stack package may be largely manufactured by a method of stacking individual semiconductor chips and then packaging stacked semiconductor chips at a time and a method of stacking individually packaged semiconductor chips. The individual semiconductor chips of the stack package are electrically connected to each other through a metal wire, a through silicon via (TSV), and the like. In particular, the stack package using the through silicon via has a structure in which the semiconductor chips are physically and electrically connected to each other vertically through the through silicon via formed in the semiconductor chip.
Meanwhile, in the semiconductor integrated circuit having the stack package structure, different chip IDs may be allocated to the stacked semiconductor chips so as to select a desired semiconductor chip among the stacked semiconductor chips. In other words, when a chip selection code is applied to the semiconductor integrated circuit from an external controller in the state in which each chip ID is allocated to the stacked semiconductor chips, a prearranged semiconductor chip may be selected based on a previously allocated chip ID.
FIG. 1 illustrates a configuration of a conventional semiconductor integrated circuit.
The present specification describes, for example, a semiconductor integrated circuit having a quad die package (QDP) in which four semiconductor chips are stacked.
Referring to FIG. 1, a semiconductor integrated circuit includes first to fourth semiconductor chips 10, 20, 30, and 40 which are vertically stacked and electrically connected to each other through first chip through via groups TSV00 and TSV01 and second chip through via groups TSV10, TSV11, TSV12, and TSV13. In this configuration, only the first semiconductor chip 10 is connected to the outside and the second to fourth semiconductor chips 20, 30, and 40 are connected to the outside through the first semiconductor chip 10.
Each of the first to fourth semiconductor chips 10, 20, 30, and 40 includes a unique ID allocation unit, a decoder, a chip selection signal input unit, and first to fourth pads. The unique ID allocation unit 11, 21, and 41 allocates its own unique ID code ID_SLICE<0:1>. The decoder 13, 23, 33, and 43 decodes the unique ID code ID_SLICE<0:1> output from the unique ID allocation unit 11, 21, 31, and 41 to generate chip ID codes DEC_SLICE<0:3>. The chip selection signal input unit 15, 25, 35, and 45 selects any one of the first to fourth chip selection signals CS0#, CS1#, CS2#, and CS3# in response to the chip ID code DEC_SLICE<0:3> and outputs the selected chip selection signal as an internal chip selection signal CS#_SEL. The first to fourth pads PD0, PD1, PD2, and PD3 receive the first to fourth chip selection signals CS0#, CS1#, CS2#, and CS3#, respectively.
In this case, the unique ID allocation unit 11, 21, 31, and 41 outputs source ID codes UP_SLICE<0:1> transferred from the unique ID allocation units of a neighboring semiconductor chip as the unique ID codes ID_SLICE<0:1 and up-counts or down-counts the unique ID codes ID_SLICE<0:1> to be transferred to another neighboring semiconductor chip through the first chip through via groups TSV00 and TSV01. For example, the unique ID allocation unit 11 included in the first semiconductor chip 10 generates the unique ID code ID_SLICE<0:1> of ‘00’ and up-counts the unique ID code ID_SLICE<0:1> to transfer a source ID code UP_SLICE<0:1 of ‘01’ to the unique ID allocation unit 21 of the second semiconductor chip 20 through the first chip through via groups TSV00 and TVS01. The unique ID allocation unit 21 included in the second semiconductor chip 20 generates a unique ID code ID_SLICE<0:1> of ‘01’ corresponding to the source ID code UP_SLICE<0:1> of ‘01’ and up-counts the unique ID code ID_SLICE<0:1> of ‘01’ to generate a source ID code UP_SLICE<0:1> of ‘10’ to be transferred to the unique ID allocation unit 31 of the third semiconductor chip 30. The unique ID allocation unit 31 included in the third semiconductor chip 30 generates a unique ID code ID_SLICE<0:1> of ‘10’ corresponding to the source ID code UP_SLICE<0:1> of ‘10’ and up-counts the unique ID code ID_SLICE<0:1> of ‘10’ to generates a source ID code UP_SLICE<0:1> of ‘11’ to be transferred to the unique ID allocation unit 41 of the fourth semiconductor chip 40. The unique ID allocation unit 41 of the fourth semiconductor chip 40 generates a unique ID code ID_SLICE<0:1> corresponding to the source ID code UP_SLICE<0:1> of ‘11’. Meanwhile, the unique ID allocation unit 11 included in the first semiconductor chip 10 is designed to generate the unique ID code ID_SLICE<0:1> of a predefined value, for example, ‘00’, as an input terminal of the source ID code UP_SLICE<0:1> floats.
In addition, the decoders 13, 23, 33, and 43 are a known technology, and therefore the detailed description thereof will be omitted.
FIG. 2 illustrates an internal configuration of the chip selection signal input unit 15, 25, 35, and 45.
Referring to FIG. 2, the chip selection signal input units 15, 25, 35, and 45 have the same configuration, and therefore only the chip selection signal input unit 15 included in the first semiconductor chip 10 will be representatively described below.
The chip selection signal input unit 15 includes first to fourth buffer units BUF0, BUF1, BUF2, and BUF3, a chip selection signal transfer unit 15_1 and an internal chip selection signal generation unit 15_3. Each of the first to fourth buffer units BUF0, BUF1, BUF2, and BUF3 is configured to buffer the first to fourth chip selection signals CS0#, CS1#, CS2#, and CS3# input through the first to fourth pads PD0, PD1, PD2, and PD3. The chip selection signal transfer unit 15_1 is configured to selectively transfer output signals of the first to fourth buffer units BUF0, BUF1, BUF2, and BUF3 in response to the chip ID codes DEC_SLICE<0:3>. The internal chip selection signal generation unit 15_3 is configured to logically combine output signals of the chip selection signal 15_1 to generate an internal chip selection signal CS#_SEL.
Herein, the chip selection signal transfer unit 15_1 includes a first path selection unit INV0 and INV1 configured to selectively transfer the output signal of the first buffer unit BUF0 in response to the first code DEC_SLICE<0> among the chip ID codes DEC_SLICE<0:3>, a second path selection unit INV2 and INV3 configured to selectively transfer the output signal of the second buffer unit BUF1 in response to the first and second codes DEC_SLICE<0> and DEC_SLICE<1> among the chip ID codes DEC_SLICE<0:3>, a third path selection unit IN4 and IN5 configured to selectively transfer the output signal of the third buffer unit BUF2 in response to the first and third codes DEC_SLICE<0> and DEC_SLICE<2> among the chip ID codes DEC_SLICE<0:3>, and a fourth path selection unit INV6 and INV7 configured to selectively transfer the output signal of the fourth buffer unit BUF3 in response to the first and fourth codes DEC_SLICE<0> and DEC_SLICE<3> among the chip ID codes DEC_SLICE<0:3>. The first to fourth path selection units INV0 and INV1, INV2 and INV3, INV4 and INV5, and INV6 and INV7 are serially connected to two inverters which are operated in response to the corresponding codes among the chip ID codes DEC_SLICE<0:3>. In this case, the output terminals BUF_CS0#, BUF_CS1#, BUF_CS2#, and BUF_CS3# of the inverters INV0, INV2, INV4, and INV6 of the front stage are connected to each other through second chip through via groups TSV10, TSV11, TSV12, and TSV13. As described above, since only the first to fourth pads PD0, PD1, PD2, and PD3 are connected to the outside, the first to fourth pads PD0, PD1, PD2, and PD3 and the first to fourth buffer units BUF0, BUF1, BUF2, and BUF3 which are included in the second to fourth semiconductor chips 20, 30, and 40 are in a floating state, such that the chip selection signal input units 25, 35, and 45 of the second to fourth semiconductor chips 20, 30, and 40 may be configured to receive the first to fourth chip selection signals BUF_CS0#, BUF_CS1#, BUF_CS2#, and BUF_CS3# buffered in the first semiconductor chip 10 through the second chip through via groups TS10, TSV11, TSV12 and TSV13.
Further, the internal chip selection signal generation unit 15_3 may include an OR gate which performs an OR operation on the output signal of the chip selection signal transfer unit 15_1.
Hereinafter, an operation of the semiconductor integrated circuit having the above-mentioned configuration will be described.
The unique ID allocation unit 11 included in the first semiconductor chip 10 has a floated input terminal to generate the unique ID code ID_SLICE<0:1> having a preset default value. For example, the unique ID allocation unit 11 generates the unique ID code ID_SLICE 0:1> of ‘00’. Next, the decoder 13 generates the chip ID code DEC_SLICE 0:3> corresponding to the unique ID code ID_SLICE<0:1>. For example, the decoder 13 generates a chip ID code DEC_SLICE<0:3> of ‘1000’ corresponding to the unique ID code ID_SLICE<0:1> of ‘00’. Therefore, the chip selection signal input unit 15 finally outputs at any one of the first to fourth chip selection signals buffered by the first to fourth buffer units BUF0, BUF1, BUF2, and BUF3 as the internal chip selection signal CS#_SEL in response to the chip ID code DEC_SLICE<0:3>. For example, the chip selection signal input unit 15 selects a first chip selection signal buffered by the first buffer unit BUF0 in response to the chip ID code DEC_SLICE<0:3> of ‘1000’ and determines whether the internal chip selection signal CS#_SEL is activated depending on whether the first chip selection signal CS0# is activated.
Meanwhile the unique ID allocation unit 11 included in the first semiconductor chip 10 outputs the source ID code UP_SLICE<0:1> generated by up-counting or down-counting the unique ID code ID_SLICE<0:1> to the second semiconductor chip 20 through the first chip through via groups TSV00 and TSV01. For example, the unique ID allocation unit 11 up-counts the unique ID code ID_SLICE<0:1> of ‘00’ to generate the source ID code UP_SLICE<0:1> of ‘01’.
Next, the unique ID allocation unit 21 included in the second semiconductor chip 20 generates the unique ID code ID_SLICE<0:1> corresponding to the source ID code UP_SLICE<0:1> output from the first semiconductor chip 11. For example, the unique ID allocation unit 21 generates the unique ID code ID_SLICE<0:1> of ‘01’. Next, the decoder 23 generates the chip ID code DEC_SLICE<0:3> corresponding to the unique ID code ID_SLICE<0:1>. For example, the decoder 23 decodes the unique ID code ID_SLICE<0:1> of ‘01’ to generate a chip ID code DEC_SLICE<0:3> of ‘0100’. Therefore, the chip selection signal input unit 25 finally outputs any one of the first to fourth chip selection signals CS0#, CS1#, CS2#, and CS3# buffered in the first semiconductor chip 10 as the internal chip selection signal CS#_SEL in response to the chip ID code DEC_SLICE<0:3>. For example, the chip selection signal input unit 25 selects the second chip selection signal buffered by the second buffer unit BUF1 in response to the chip ID code DEC_SLICE<0:3> of ‘0100’ and determines whether the internal chip selection signal CS#_SEL is activated depending on whether the second chip selection signal CS1# is activated.
Meanwhile, the unique ID allocation unit 21 included in the second semiconductor chip 20 outputs the source ID code UP_SLICE<0:1> generated by up-counting or down-counting the unique ID code ID_SLICE<0:1> to the third semiconductor chip 30 through the first chip through via groups TSV00 and TSV01. For example, the unique ID allocation unit 21 up-counts the unique ID code ID_SLICE<0:1> of ‘01’ to generate the source ID code UP_SLICE<0:1> of ‘10’.
Next, the unique ID allocation unit 31 included in the third semiconductor chip 30 generates the unique ID code ID_SLICE 0:1> corresponding to the source ID code UP_SLICE<0:1> output from the second semiconductor chip 21. For example, the unique ID allocation unit 31 generates the unique ID code ID_SLICE<0:1> of ‘10’. Next, the decoder 33 generates the chip ID code DEC_SLICE 0:3> corresponding to the unique ID code ID_SLICE<0:1>. For example, the decoder 33 decodes the unique ID code ID_SLICE<0:1> of ‘10’ to generate a chip ID code DEC_SLICE<0:3> of ‘0010’. Therefore, the chip selection signal input unit 35 finally outputs any one of the first to fourth chip selection signals CS0#, CS1#, CS2#, and CS3# buffered in the first semiconductor chip 10 as the internal chip selection signal CS#_SEL in response to the chip ID code DEC_SLICE<0:3>. For example, the chip selection signal input unit 35 selects a third chip selection signal buffered by the third buffer unit BUF2 in response to a chip ID code DEC_SLICE<0:3> of ‘0010’ and determines whether the internal chip selection signal CS#_SEL is activated depending on whether the third chip selection signal CS2# is activated.
Meanwhile, the unique ID allocation unit 31 included in the third semiconductor chip 30 outputs the source ID code UP_SLICE<0:1> generated by up-counting or down-counting the unique ID code ID_SLICE<0:1> to the fourth semiconductor chip 40 through the first chip through via groups TSV00 and TSV01. For example, the unique ID allocation unit 31 up-counts the unique ID code ID_SLICE<0:1> of ‘10’ to generate a source ID code UP_SLICE<0:1> of ‘11’.
Finally, the unique ID allocation unit 41 included in the fourth semiconductor chip 40 generates the unique ID code ID_SLICE<0:1 corresponding to the source ID code UP_SLICE<0:1> output from the third semiconductor chip 30. For example, the unique ID allocation unit 41 generates a unique ID code ID_SLICE<0:1> of ‘11’. Next, the decoder 43 generates a chip ID code DEC_SLICE 0:3> corresponding to the unique ID code ID_SLICE<0:1>. For example, the decoder 43 decodes the unique ID code ID_SLICE<0:1> of ‘11’ to generate a chip ID code DEC_SLICE<0:3> of ‘0001’. Therefore, the chip selection signal input unit 45 finally outputs any one of the first to fourth chip selection signals CS#, CS#1, CS2#, and CS3# buffered in the first semiconductor chip 10 as the internal chip selection signal CS#_SEL in response to the chip ID code DEC_SLICE<0:3>. For example, the chip selection signal input unit 45 selects the fourth chip selection signal buffered by the fourth buffer unit BUF3 in response to the chip ID code DEC_SLICE 0:3> of ‘0001’ and determines whether the internal chip selection signal CS#_SEL is activated depending on whether the fourth chip selection signal CS3# is activated.
The semiconductor integrated circuit having the above-mentioned configuration allocates chip IDs to each semiconductor chip 10, 20, 30, and 40, thereby easily transferring the chip selection signals allocated to each semiconductor chip 10, 20, 30, and 40.
However, when any one of the semiconductor chips 10, 20, 30, and 40 fails, the semiconductor integrated circuit may not use the remaining semiconductor chips. This is because the chip ID code DEC_SLICE<0:3> is fixedly allocated to each semiconductor chip 10, 20, 30, and 40. For example, when the third semiconductor chip 30 or the fourth semiconductor chip 40 fails, the first and second semiconductor chips 10 and 20 may be used as a double die package (DDP), but when the second semiconductor chip 20 fails, the first and second semiconductor chips 10 and 20 may not used as the double die package (DDP).